One of the requirements or goals for a fast, static MOS random access memory (SRAM) is that these devices have a sufficiently fast recovery from a write cycle that the effective cycle time for a read cycle is the same regardless of whether it follows a read or a write cycle. As memories become more dense, the bit line equalization schemes used in prior art devices for recovering from write cycles have become insufficient to overcome the increasing capacitances encountered in high density, high speed SRAMs.
To achieve fast access times in high density memories, many memory devices use smaller numbers of memory cells per column than previous generations of SRAMs in order to lower the capacitance of each bit line, because this increases the speed at which data is transferred from a memory cell to the bit lines. As a result, the number of memory columns in SRAM devices has increased more than the densities of the SRAM devices. For example, a 16K SRAM may use columns with 128 memory cells on each of 128 columns, while a 64K SRAM may use 64 memory cells on each of 1024 columns resulting in an eight-fold increase in the number of columns for a four-fold increase in memory density.
Since there must be one equalization transistor for every column of memory cells, the number of equalization transistors has increased dramatically in some high density SRAM devices. As a result, the total capacitance of the equalization transistors has become sufficiently large that it can significantly slow down the bit line equalization process.
Referring to FIG. 1 in the first generation of fast, static MOS RAMs (SRAMs), fast access time was achieved by the use of d.c. (NMOS depletion mode) pull-ups 20 and 22 on the bit lines BL and BLB to limit signal swing during read operations. This limited the amount of voltage differential (sometimes called slew) which the memory cells needed to generate on the bit lines BL-BLB and common data out lines CDO-CDOB.
One major problem with this approach is that these memory devices have long write recovery times (i.e., the access time of the first read after a write operation), because the bit line pull-ups 20 and 22 must overcome a much larger bit line voltage differential after a write operation than after a read operation. This makes the effective cycle time for alternating read and write cycles longer than is possible for successive read cycles or for successive write cycles.
Another penalty imposed by the use of d.c. bit line pull-ups is the contention between the pull-up devices and the pull-down devices 24 and 26 used during write cycles. This extends the length of time required to write data into the memory, and more importantly, wastes a considerable amount of power. In fact, the amount of power wasted during writing and reading has made this approach unsuitable for use in higher density memories.
Referring to FIG. 2, more recent, asynchronous fast static RAMs have used address transition detection (ATD) to generate bit line equalization signals EQ and EQB, and to temporarily disable the sense amplifier clock signal SA at the beginning of memory access cycles, thereby allowing the use of higher impedance bit line loads - or no d.c. loads at all. This has reduced the average power consumed and also the minimum required write pulse (i.e, the length of time required to write data into the memory).
One penalty of this approach is the large I.sub.cc current spike during equalization. For example, this current spike would exceed one ampere for a device with 256 bit lines each having a capacitance of four picofarads, a maximum voltage swing of three volts, and a three nanosecond bit line equalization time: ##EQU1## While there are techniques to reduce various components of this current spike, it is clear that as memories become faster and denser, this problem becomes more severe.
An even more critical penalty of address transition detection for fast, high density static RAMs is delays in the memory's access time. By requiring bit line equalization in the beginning of the access cycle, several delays are inserted into the critical timing path. Address transition has to be logically detected and then buffered to drive the large capacitive load of all the equalization, pull-up, and sense amp transistors gated by the derivatives of the address transition detection (ATD) signal. Also, the equalization signal pulses must be wide enough at their destinations to guarantee adequate equalization of the bit lines. The sum of all these delays can be a significant portion (e.g., thirty to forty percent) of the memory's access time.
The present invention provides a method of recovering from write cycles by automatically equalizing bit line voltages at the end of write cycles, instead of equalizing bit line voltages at the beginning of the next read cycle. In addition, using a memory architecture with a multiplicity of separately accessed memory blocks, the bit line equalization transistors are enabled using decoded write recovery equalization pulses so that only bit lines in the memory block which was written into are equalized after the completion of each write cycle. This reduces the delays caused by the high total capacitance of the equalization transistors and reduces the current spike associated with equalizing the bit lines because only a small fraction of the bit lines are affected by the equalization process.
Another aspect of the present invention concerns problems with the use of common data out lines in high density SRAMs. Common data out lines are lines which couple a selected pair of bit lines to a sense amplifier. Thus they act as the common output path for a multiplicity of bit lines. In some memory devices, these lines act as common data lines for both reading and writing data and are therefore called "common data lines" in those devices. The present invention can be used with both types of common data lines.
As the density of fast SRAMs continues to increase, the capacitance of the bit lines and common data out lines increases proportionately, thereby increasing the time required to generate an adequate differential signal to be read by a sense amplifier, and also the time required to write an adequate signal into a memory cell.
The present invention solves these problems by providing mechanisms for reducing the voltage swings on the bit lines during read cycles, and for equalizing the common data out lines at the end of each read cycle, thereby eliminating a significant delay in the memory access paths of prior art static RAM devices.